1. Field of the Invention
The present invention relates to ESD protection circuits, and more particularly to a power switch embedded in an ESD pad.
2. Description of the Prior Art
Flash memory is a type of non-volatile memory commonly employed in memory cards, flash drives, and portable electronics for providing data storage and transfer. Flash memory may be electrically written to, erased, and reprogrammed to allow deletion of data and writing of new data. Some advantages of flash memory include fast read access time, and shock resistance. Flash memory is also very resistant to pressure and temperature variations.
Please refer to FIG. 1, which is a diagram of a flash memory circuit 10. The flash memory circuit 10 includes a plurality of flash memory blocks 100 that are programmable through a programming voltage VPP applied at a pad VPP_PAD. A gate driving circuit 110 drives gate terminals of a first transistor 131 and a second transistor 132 of a pass gate 130 to allow the programming voltage VPP to be sent to the flash memory blocks 100. When the programming voltage VPP is applied at the pad VPP_PAD, the programming voltage VPP is received by an inverter 120 through a resistor R at a node G2. The inverter 120 comprises a pull-up transistor MP, and a pull-down transistor MN. The programming voltage is also applied to a gate terminal of the first transistor 131 of the pass gate, and the pull-down transistor MN is turned on by the pad voltage to pull down voltage applied to a gate terminal of the second transistor 132 of the pass gate 130. Thus, the pass gate 130 turns on, and the programming voltage VPP may be sent to the flash memory blocks 100.
Electrostatic discharge (ESD) entering the flash memory circuit 10 through the pad VPP_PAD is one potential source of damage to the flash memory blocks 100. To mitigate the ESD effect, one goal is to direct excess charges to a lower potential node, such as a node VSS. The flash memory circuit 10 thus further comprises an ESD transistor M_ESD for redirecting ESD current away from the flash memory blocks 100. When the voltage applied to the pad VPP_PAD goes high, agate terminal of the ESD transistor M_ESD is temporarily pulled high at a node G1 through the second transistor MP, because a MOS capacitor NC and a resistor R keep gates of the first transistor MN and the second transistor MP low while the MOS capacitor NC is charged by the ESD charges. ESD zapping typically occurs for a period on the order of nanoseconds. Thus, the resistor R and the MOS capacitor NC may be designed with a RC time constant of approximately 1 us to keep the ESD transistor M_ESD turned on long enough to redirect most or all of the ESD current. One disadvantage of the flash memory circuit 10 is that the pad VPP_PAD cannot be utilized as an I/O pad.